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| 1 ltc4007 4007i 4a, high efficiency, standalone li battery charger january 2003 n complete charger controller for 3- or 4-cell lithium-ion batteries n high conversion efficiency: up to 96% n output currents exceeding 4a n 0.8% charging voltage accuracy n built-in charge termination for li-ion batteries n ac adapter current limiting maximizes charge rate* n thermistor input for temperature qualified charging n wide input voltage range: 6v to 28v n 0.5v dropout voltage; maximum duty cycle: 98% n programmable charge current: 5% accuracy n indicator outputs for charging, c/10 current detection, ac adapter present, low battery, input current limiting and faults n charging current monitor output n available in a 24-pin narrow ssop package n notebook computers n portable instruments n battery-backup systems n standalone li-ion chargers , ltc and lt are registered trademarks of linear technology corporation. features descriptio n u applicatio s u final electrical specifications information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. typical applicatio u 12.6v, 4a li-ion battery charger the ltc ? 4007 is a complete constant-current/constant- voltage charger controller for 3- or 4-cell lithium-ion batteries. the pwm controller uses a synchronous, quasi- constant frequency, constant off-time architecture that will not generate audible noise even when using ceramic capacitors. charging current is programmable to 5% accuracy using a programming resistor. charging current can also be monitored as a voltage across the program- ming resistor. the output float voltage is pin programmed for cell count (3 cells or 4 cells) and chemistry (4.2v/4.1v). a timer, programmed by an external resistor, sets the total charge time. charging is automatically restarted when cell voltage falls below 3.9v/cell. ltc4007 includes a thermistor input, which suspends charging if an unsafe temperature condition is detected. if the cell voltage is less than 2.5v, a low-battery indicator asserts and can be used to program a trickle charge cur- rent to safely charge depleted batteries. the fault pin is also asserted and charging terminates if the low-battery condition persists for more than 1/4 of the total charge time. 3c4c chem lobat i cl acp shdn fault chg flag ntc r t lobat i cl acp shdn fault chg flag dcin infet clp cln tgate bgate pgnd csp bat prog ith gnd ltc4007 32.4k 309k 0.47 f thermistor 10k ntc timing resistor (~2 hours) 100k 100k 100k v logic dcin 0v to 28v 0.1 f input switch 15nf q1 q2 20 f 10 h 4.9k 3.01k 3.01k 0.025 0.025 20 f li-ion battery charging current monitor q1: si4431dy q2: fdc6459 system load 0.12 f 6.04k 26.7k 0.0047 f 4007 ta01 *u.s. patent no. 5,723,970
2 ltc4007 4007i 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 dcin chg acp r t fault gnd 3c4c lobat ntc ith prog nc shdn infet bgate pgnd tgate cln clp flag chem bat csp i cl (note 1) voltage from dcin, clp, cln to gnd ....... + 32v/C 0.3v pgnd with respect to gnd ................................. 0.3v csp, bat to gnd ....................................... +28v/C 0.3v chem, 3c4c, r t to gnd .............................. +7v/C 0.3v ntc ............................................................ +10v/C 0.3v acp, shdn, chg, flag, fault, lobat, i cl .............................................. + 32v/C 0.3v operating ambient temperature range (note 4) ............................................. C 40 c to 85 c operating junction temperature ......... C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number ltc4007egn t jmax = 125 c, q ja = 90 c/w the l denotes specifications which apply over the full operating temperature range (note 4), otherwise specifications are at t a = 25 c. v dcin = 20v, v bat = 12v unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. electrical characteristics symbol parameter conditions min typ max units dcin operating range 628v i q operating current sum of current from clp, cln , dcin 3 5 ma v tol charge voltage accuracy nominal values: 12.3v, 12.6v, 16.4v, 16.8v C0.8 0.8 % (note 2) l C1.0 1.0 % i tol charge current accuracy (note 3) v csp C v bat target = 100mv C 4 4 % l C5 5 % v bat < 6v, v csp C v bat target = 10mv C60 60 % 6v v bat v lobat , v csp C v bat C35 35 % target = 10mv t tol termination timer accuracy r rt = 270k l C15 15 % shutdown battery leakage current dcin = 0v l 15 30 m a shdn = 3v l C10 10 m a uvlo undervoltage lockout threshold dcin rising, v bat = 0 l 4.2 4.7 5.5 v shutdown threshold at shdn l 1 1.6 2.5 v shdn pin current C10 m a operating current in shutdown v shdn = 0v, sum of current from clp, 2 3 ma cln, dcin current sense amplifier, ca1 input bias current into bat pin 11.67 m a cmsl ca1/i 1 input common mode low l 0v cmsh ca1/i 1 input common mode high l v cln C 0.2 v 3 ltc4007 4007i the l denotes specifications which apply over the full operating temperature range (note 4), otherwise specifications are at t a = 25 c. v dcin = 20v, v bat = 12v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units current comparators i cmp and i rev i tmax maximum current sense threshold (v csp C v bat )v ith = 2.4v l 140 165 200 mv i trev reverse current threshold (v csp C v bat ) C30 mv current sense amplifier, ca2 transconductance 1 mmho source current measured at i th , v ith = 1.4v C 40 m a sink current measured at i th , v ith = 1.4v 40 m a current limit amplifier transconductance 1.4 mmho v clp current limit threshold l 93 100 107 mv i clp clp input bias current 100 na voltage error amplifier, ea transconductance 1 mmho sink current measured at i th , v ith = 1.4v 36 m a ovsd overvoltage shutdown threshold as a percent l 102 107 110 % of programmed charger voltage input p-channel fet driver (infet) dcin detection threshold (v dcin C v cln ) dcin voltage ramping up l 0 0.17 0.25 v from v cln C 0.1v forward regulation voltage (v dcin C v cln ) l 25 50 mv reverse voltage turn-off voltage (v dcin C v cln ) dcin voltage ramping down l C60 C25 mv infet on clamping voltage (v dcin C v infet )i infet = 1 m a l 5 5.8 6.5 v infet off clamping voltage (v dcin C v infet )i infet = C 25 m a 0.25 v thermistor ntcvr reference voltage during sample time 4.5 v high threshold v ntc rising l ntcvr ntcvr ntcvr v ? 0.48 ? 0.5 ? 0.52 low threshold v ntc falling l ntcvr ntcvr ntcvr v ? 0.115 ? 0.125 ? 0.135 thermistor disable current v ntc 10v 10 m a indicator outputs (acp, chg, flag, lobat, i cl , fault c10tol flag (c/10) accuracy voltage falling at prog l 0.375 0.397 0.420 v lbtol lobat threshold accuracy 3c4c = 0v, chem = 0v l 7.10 7.32 7.52 v 3c4c = 0v, chem = open l 7.27 7.50 7.71 v 3c4c = open, chem = 0v l 9.46 9.76 10.10 v 3c4c = open, chem = open l 9.70 10 10.28 v restart threshold accuracy 3c4c = 0v, chem = 0v l 11.13 11.42 11.65 v 3c4c = 0v, chem = open l 11.40 11.70 11.94 v 3c4c = open, chem = 0v l 14.84 15.23 15.54 v 3c4c = open, chem = open l 15.20 15.60 15.92 v i cl threshold accuracy 83 93 1o5 mv 4 ltc4007 4007i the l denotes specifications which apply over the full operating temperature range (note 4), otherwise specifications are at t a = 25 c. v dcin = 20v, v bat = 12v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: see test circuit. note 3: does not include tolerance of current sense resistor or current programming resistor. note 4: the ltc4007e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. electrical characteristics symbol parameter conditions min typ max units v ol low logic level of acp, chg, flag, lobat, i ol = 100 m a l 0.5 v i cl , fault v oh high logic level of chg, lobat, i cl i oh = C1 m a l 2.7 v i off off state leakage current of acp, flag, fault v oh = 3v C1 1 m a i po pull-up current on chg, lobat, i cl v = 0v C10 m a timer defeat threshold at chg 1 v programming inputs (chem and 3c4c) v ih high logic level l 3.3 v v il low logic level l 1v i pi pull-up current v = 0v C 14 m a oscillator f osc regulator switching frequency 255 300 345 khz f min regulator switching frequency in drop out duty cycle 3 98% 20 25 khz dc max regulator maximum duty cycle v csp = v bat 98 99 % gate drivers (tgate, bgate) v tgate high (v cln C v tgate )i tgate = C1ma 50 mv v bgate high c load = 3000pf 4.5 5.6 10 v v tgate low (v cln C v tgate )c load = 3000pf 4.5 5.6 10 v v bgate low i bgate = 1ma 50 mv tgate transition time tgtr tgate rise time c load = 3000pf, 10% to 90% 50 110 ns tgtf tgate fall time c load = 3000pf, 10% to 90% 50 100 ns bgate transition time bgtr bgate rise time c load = 3000pf, 10% to 90% 40 90 ns bgtf bgate fall time c load = 3000pf, 10% to 90% 40 80 ns v tgate at shutdown (v cln C v tgate )i tgate = C1 m a, dcin = 0v, cln = 12v 100 mv v bgate at shutdown i bgate = 1 m a, dcin = 0v, cln = 12v 100 mv 5 ltc4007 4007i uu u pi fu ctio s dcin (pin 1): external dc power source input. bypass this pin with at least 0.01 m f. see applications information. chg (pin 2): charge status output. when the battery is being charged, the chg pin is pulled low by an internal n-channel mosfet. internal 10 m a pull-up to 3.5v. if v logic is greater than 3.3v, add an external pull-up. the timer function can be defeated by forcing this pin below 1v (or connecting it to gnd). acp(pin 3): open-drain output to indicate if the ac adapter voltage is adequate for charging. this pin is pulled low by an internal n-channel mosfet if dcin is below bat. a pull-up resistor is required. the pin is capable of sinking at least 100 m a. r t (pin 4): timer resistor. the timer period is set by placing a resistor, r rt , to gnd. this resistor is always required. the timer period is t timer = (1hour ? r rt /154k). fault (pin 5): active low open-drain output that indi- cates charger operation has stopped due to a low-battery conditioning error, or that charger operation is suspended due to the thermistor exceeding allowed values. a pull-up resistor is required if this function is used. the pin is capable of sinking at least 100 m a. gnd (pin 6): ground for low power circuitry. 3c4c (pin 7): select 3-cell or 4-cell float voltage by connecting this pin to gnd or open, respectively. internal 14 m a pull-up to 5.3v. this pin can also be driven with open-collector/drain logic levels. high: 4 cell. low: 3 cell. lobat (pin 8): low-battery indicator. active low digital output. internal 10 m a pull-up to 3.5v. if the battery voltage is below 2.5v/cell (or 2.44v/cell for 4.1v chemis- try batteries) lobat will be low. the pin is capable of sinking at least 100 m a. if v logic is greater than 3.3v, add an external pull-up. ntc (pin 9): a thermistor network is connected from ntc to gnd. this pin determines if the battery temperature is safe for charging. the charger and timer are suspended and the fault pin is driven low if the thermistor indicates a temperature that is unsafe for charging. the thermistor function may be disabled with a 300k to 500k resistor from dcin to ntc. ith (pin 10): control signal of the inner loop of the current mode pwm. higher ith voltage corresponds to higher charging current in normal operation. a 6k resistor, in series with a capacitor of at least 0.1 m f to gnd provides loop compensation. typical full-scale output current is 40 m a. nominal voltage range for this pin is 0v to 3v. prog (pin 11): current programming/monitoring input/ output. an external resistor to gnd programs the peak charging current in conjunction with the current sensing resistor. the voltage at this pin provides a linear indication of charging current. peak current is equivalent to 1.19v. zero current is approximately 0.3v. a capacitor from prog to ground is required to filter higher frequency components. the maximum resistance to ground is 100k. values higher than 100k can cause the charger to shut down. nc (pin 12): no connect. i cl (pin 13): input current limit indicator. active low digital output. internal 10 m a pull-up to 3.5v. pulled low if the charger current is being reduced by the input current limiting function. the pin is capable of sinking at least 100 m a. if v logic is greater than 3.3v, add an external pull-up. csp (pin 14): current amplifier ca1 input. the csp and bat pins measure the voltage across the sense resistor, r sense , to provide the instantaneous current signals re- quired for both peak and average current mode operation. 6 ltc4007 4007i uu u pi fu ctio s bat (pin 15): battery sense input and the negative reference for the current sense resistor. a precision internal resistor divider sets the final float potential on this pin. the resistor divider is disconnected during shutdown. chem (pin 16): select 4.1v or 4.2v cell chemistry by connecting the pin to gnd or open, respectively. internal 14 m a pull-up to 5.3v. can also be driven with open- collector/drain logic levels. flag (pin 17): active low open-drain output that indi- cates when charging current has declined to 10% of maximum programmed current. a pull-up resistor is required if this function is used. the pin is capable of sinking at least 100 m a. clp (pin 18): positive input to the supply current limiting amplifier, cl1. the threshold is set at 100mv above the voltage at the cln pin. when used to limit supply current, a filter is needed to filter out the switching noise. if no current limit function is desired, connect this pin to cln. cln (pin 19): negative reference for the input current limit amplifier, cl1. this pin also serves as the power supply for the ic. a 10 m f to 22 m f bypass capacitor should be connected as close as possible to this pin. tgate (pin 20): drives the top external p-channel mosfet of the battery charger buck converter. pgnd (pin 21): high current ground return for the bgate driver. bgate (pin 22): drives the bottom external n-channel mosfet of the battery charger buck converter. infet (pin 23): drives the gate of the external input pfet. shdn (pin 24): charger is shut down and timer is reset when this pin is high. internal 10 m a pull-up to 3.5v. this pin can also be used to reset the charger by applying a positive pulse that is a minimum of 0.1 m s long. 7 ltc4007 4007i block diagra w + + 7 6 16 9k 1.19v 11.67 a tbad restart mux 1.105v ea g m = 1m g m = 1m g m = 1.4m 708mv 1.19v 3c4c flag gnd chem 8 lobat 13 20 i cl tgate bgate q1 q2 18 clp 100mv 15nf 20 f r cl 5k 19 cln 22 pgnd l1 397mv chg r t ntc 0.47 f 10k ntc r rt + + cl1 timer/controller thermistor oscillator 2 4 9 bat 3k r sense csp ith 10 32.4k watchdog detect t off cln dcin ov oscillator 1.28v pwm logic s r q charge i rev + i cmp + 5 buffered ith 21 prog 4007 bd r prog 26.7k 0.0047 f 11 17 fault 5 shdn 24 acp 3 infet q3 dcin 0.1 f v in 23 1 + cln 5.8v 3k 20 f 6k 0.12 f 15 14 + ca1 ca2 + + c/10 35mv + + 17mv 8 ltc4007 4007i test circuit + + ea lt1055 ltc4007 v ref chem 3c4c bat divider/ mux 16 7 15 ith 0.6v 4007 tc 10 operatio u overview the ltc4007 is a synchronous current mode pwm step- down (buck) switcher battery charger controller. the charge current is programmed by the combination of a program resistor (r prog ) from the prog pin to ground and a sense resistor (r sense ) between the csp and bat pins. the final float voltage is programmed to one of four values (12.3v, 12.6v, 16.4v, 16.8v) with 1% maximum accuracy using pins 3c4c and chem. charging begins when the potential at the dcin pin rises above the voltage at bat (and the uvlo voltage) and the shdn pin is low; the chg pin is set low. at the beginning of the charge cycle, if the cell voltage is below 2.5v (2.44v if chem is low), the lobat pin will be low. the lobat indicator can be used to reduce the charging current to a low value, typically 10% of full scale. if the cell voltage stays below 2.5v for 25% of the total charge time, the charge sequence will be terminated immediately and the fault pin will be set low. an external thermistor network is sampled at regular intervals. if the thermistor value exceeds design limits, charging is suspended and the fault pin is set low. if the thermistor value returns to an acceptable value, charging resumes and the fault pin is set high. an external resistor on the r t pin sets the total charge time. the timer can be defeated by forcing the chg pin to a low voltage. as the battery approaches the final float voltage, the charge current will begin to decrease. when the current drops to 10% of the full-scale charge current, an internal c/10 comparator will indicate this condition by latching the flag pin low. the charge timer is also reset to 1/4 of the total charge time when flag goes low. if this condition is caused by an input current limit condition, described below, then the flag indicator will be inhibited. when a time-out occurs, charging is terminated immediately and the chg pin is forced to a high impedance state. the charger will automatically restart if the cell voltage is below 3.9v (or 3.81v if chem is low). to restart the charge cycle manually, simply remove the input voltage and reapply it, or set the shdn pin high momentarily. when the input voltage is not present, the charger goes into a sleep mode, dropping battery current drain to 15 m a. this greatly reduces the current drain on the battery and increases the standby time. the charger is inhibited any time the shdn pin is high. input fet the input fet circuit performs two functions. it enables the charger if the input voltage is higher than the cln pin and provides the logic indicator of ac present on the acp pin. it controls the gate of the input fet to keep a low forward voltage drop when charging and also prevents reverse current flow through the input fet. if the input voltage is less than v cln , it must go at least 170mv higher than v cln to activate the charger. when this occurs the acp pin is released and pulled up with an external load to indicate that the adapter is present. the 9 ltc4007 4007i gate of the input fet is driven to a voltage sufficient to keep a low forward voltage drop from drain to source. if the voltage between dcin and cln drops to less than 25mv, the input fet is turned off slowly. if the voltage between dcin and cln is ever less than C 25mv, then the input fet is turned off in less than 10 m s to prevent significant reverse current from flowing in the input fet. in this condition, the acp pin is driven low and the charger is disabled. battery charger controller the ltc4007 charger controller uses a constant off-time, current mode step-down architecture. during normal op- eration, the top mosfet is turned on each cycle when the oscillator sets the sr latch and turned off when the main current comparator i cmp resets the sr latch. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current trips the current comparator i rev or the beginning of the next cycle. the oscillator uses the equation: t vv vf off dcin bat dcin osc = to set the bottom mosfet on time. the result is a nearly constant switching frequency over a wide input/output voltage range. this activity is diagrammed in figure 1. tgate off on bgate inductor current t off trip point set by ith voltage on off 4006 f01 figure 1 operatio u table 1. truth table for indicator states timer mode dcin shdn acp** lobat flag** fault** i cl state chg** shut down by low adapter voltage 11 ltc4007 4007i operatio u clk (not to scale) v ntc t sample voltage across thermistor t hold 4007 f04 comparator high limit comparator low limit figure 4 6 ntc ltc4007 s1 r9 32.4k c7 0.47 f r th 10k ntc + + + 60k ~4.5v clk 45k 15k tbad 4007 f03 d c q figure 3 the timing resistor connected to r t , keeps switch s1 closed to sample the thermistor: t sample = 127.5 ? 20 ? r rt ? 17.5pf = 16.2ms, for r rt = 309k the external rc network is driven to approximately 4.5v and settles to a final value across the thermistor of: v vr rr rth final th th () . = + 45 9 this voltage is stored by c7. then the switch is opened for a short period of time to read the voltage across the thermistor. t hold = 10 ? r rt ? 17.5pf = 64 m s, for r rt = 309k when the t hold interval ends the result of the thermistor testing is stored in the d flip-flop (dff). if the voltage at ntc is within the limits provided by the resistor divider feeding the comparators, then the nor gate output will be low and the dff will set t bad to zero and charging will continue. if the voltage at ntc is outside of the resistor divider limits, then the dff will set t bad to one, the charger will be shut down, fault pin is set low and the timer will be suspended until t bad returns to zero (see figure 4). 12 ltc4007 4007i applicatio s i for atio wu uu battery detection it is generally not good practice to connect a battery while the charger is running. the timer is in an unknown state and the charger could provide a large surge current into the battery for a brief time. the figure 5 circuit keeps the charger shut down and the timer reset while a battery is not connected. increased to reduce the ripple caused by the r prog switching. the compensation capacitor at ith will prob- ably need to be increased also to improve stability and prevent large overshoot currents during start-up condi- tions. charging current will be proportional to the duty cycle of the switch with full current at 100% duty cycle and zero current when q1 is off. maintaining c/10 accuracy the c/10 comparator threshold that drives the flag pin has a fixed threshold of approximately v prog = 400mv. this threshold works well when r prog is 26.7k, but will not yield a 10% charging current indication if r prog is a different value. there are situations where a standard value of r sense will not allow the desired value of charging current when using the preferred r prog value. in these cases, where the full-scale voltage across r sense is within 20mv of the 100mv full-scale target, the input resistors connected to csp and bat can be adjusted to provide the desired maximum programming current as well as the correct flag trip point. for example, the desired max charging current is 2.5a but the best r sense value is 0.033 w . in this case, the voltage across r sense at maximum charging current is only 82.5mv, normally r prog would be 30.1k but the nominal flag trip point is only 5% of maximum charging current. if the input resistors are reduced by the same amount as the full-scale voltage is reduced then, r4 = r5 = 2.49k and r prog = 26.7k, the maximum charging current is still 2.5a but the flag trip point is maintained at 10% of full scale. there are other effects to consider. the voltage across the current comparator is scaled to obtain the same values as the 100mv sense voltage target, but the input referred 1 dcin ltc4007 adapter power switch closed when battery connected 24 shdn 4007 f05 figure 5 charger current programming the basic formula for charging current is: i vkr v r charge max ref prog sense () / . = w 3 0 035 v ref = 1.19v this leaves two degrees of freedom: r sense and r prog . the 3k input resistors must not be altered since internal currents and voltages are trimmed for this value. pick r sense by setting the average voltage between c sp and bat to be close to 100mv during maximum charger current. then r prog can be determined by solving the above equation for r prog . r vk ri v prog ref sense charge max = w + . () 3 0 035 table 2. recommended r sns and r prog resistor values i max (a) r sense ( w ) 1% r sense (w) r prog (k w ) 1% 1.0 0.100 0.25 26.7 2.0 0.050 0.25 26.7 3.0 0.033 0.5 26.7 4.0 0.025 0.5 26.7 charging current can be programmed by pulse width modulating r prog with a switch q1 to r prog at a fre- quency higher than a few khz (figure 6). c prog must be figure 6. pwm current programming r z 102k c prog 4007 f06 prog 11 ltc4007 q1 2n7002 r prog 0v 5v 13 ltc4007 4007i sense voltage is reduced, causing some careful consider- ation of the ripple current. input referred maximum com- parator threshold is 117mv, which is the same ratio of 1.4x the dc target. input referred i rev threshold is scaled back to C24mv. the current at which the switcher starts will be reduced as well so there is some risk of boost activity. these concerns can be addressed by using a slightly larger inductor to compensate for the reduction of tolerance to ripple current. charger voltage programming pins chem and c3c4 are used to program the charger final output voltage. the chem pin programs li-ion battery chemistry for 4.1v/cell (low) or 4.2v/cell (high). the c3c4 pin selects either 3 series cells (low) or 4 series cells (high). it is recommended that these pins be shorted to ground (logic low) or left open (logic high) to effect the desired logic level. use open-collector or open-drain out- puts when interfacing to the chem and 3c4c pins from a logic control circuit. table 3. charger voltage programming v final (v) 3c4c chem 12.3 low low 12.6 low high 16.4 high low 16.8 high high setting the timer resistor the charger termination timer is designed for a range of 1hour to 3 hour with a 15% uncertainty. the timer is programmed by the resistor r rt using the following equation: t timer = 2 27 ? r rt ? 175pf it is important to keep the parasitic capacitance on the r t pin to a minimum. the trace connecting r t to r rt should be as short as possible. soft-start the ltc4007 is soft started by the 0.12 m f capacitor on the ith pin. on start-up, ith pin voltage will rise quickly to 0.5v, then ramp up at a rate set by the internal 40 m a pull- up current and the external capacitor. battery charging applicatio s i for atio wu uu current starts ramping up when ith voltage reaches 0.8v and full current is achieved with ith at 2v. with a 0.12 m f capacitor, time to reach full charge current is about 2ms and it is assumed that input voltage to the charger will reach full value in less than 2ms. the capacitor can be increased up to 1 m f if longer input start-up times are needed. input and output capacitors the input capacitor (c2) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. worst-case rms ripple current will be equal to one half of output charging current. actual capacitance value is not critical. solid tantalum low esr capacitors have high ripple current rating in a rela- tively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass . high input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. solid tantalum capaci- tors have a known failure mechanism when subjected to very high turn-on surge currents. only kemet t495 series of surge robust low esr tantalums are rated for high surge conditions such as battery to ground. the relatively high esr of an aluminum electrolytic for c1, located at the ac adapter input terminal, is helpful in reducing ringing during the hot-plug event. refer to an88 for more information. figure 7. t timer vs r rt r rt (k ) 100 0 t timer (minutes) 20 60 80 100 200 140 200 300 350 4007 f07 40 160 180 120 150 250 400 450 500 14 ltc4007 4007i highest possible voltage rating on the capacitor will mini- mize problems. consult with the manufacturer before use. alternatives include new high capacity ceramic (at least 20 m f) from tokin, united chemi-con/marcon, et al. other alternative capacitors include os-con capacitors from sanyo. the output capacitor (c3) is also assumed to absorb output switching current ripple. the general formula for capacitor current is: i v v v lf rms bat bat dcin = () ? ? ? ? ()() 029 1 1 . for example: v dcin = 19v, v bat = 12.6v, l1 = 10 m h, and f = 300khz, i rms = 0.41a. emi considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300khz switching frequency. switching ripple current splits be- tween the battery and the output capacitor depending on the esr of the output capacitor and the battery imped- ance. if the esr of c3 is 0.2 w and the battery impedance is raised to 4 w with a bead or inductor, only 5% of the current ripple will flow in the battery. inductor selection higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency gener- ally results in lower efficiency because of mosfet gate charge losses. in addition, the effect of inductor value on ripple current and low current operation must also be considered. the inductor ripple current d i l decreases with higher frequency and increases with higher v in . d= ()( ) ? ? ? ? i fl v v v l out out in 1 1 accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.4(i max ). in no case should d i l exceed 0.6(i max ) due to limits imposed by i rev and ca1. remember the maximum d i l occurs at the maxi- mum input voltage. in practice 10 m h is the lowest value recommended for use. lower charger currents generally call for larger inductor values. use table 4 as a guide for selecting the correct inductor value for your application. table 4 max average minimum inductor current (a) input voltage (v) value ( m h) 1 20 40 20% 1>2056 20% 2 20 20 20% 2>2030 20% 3 20 15 20% 3>2020 20% 4 20 10 20% 4>2015 20% charger switching power mosfet and diode selection two external power mosfets must be selected for use with the charger: a p-channel mosfet for the top (main) switch and an n-channel mosfet for the bottom (syn- chronous) switch. the peak-to-peak gate drive levels are set internally. this voltage is typically 6v. consequently, logic-level threshold mosfets must be used. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , total gate capacitance qg, reverse transfer capacitance c rss , input voltage and maximum output current. the charger is operating in continuous mode at moderate to high currents so the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out /v in synchronous switch duty cycle = (v in C v out )/v in . applicatio s i for atio wu uu 15 ltc4007 4007i the mosfet power dissipations at maximum output current are given by: pmain = v out /v in (i max ) 2 (1 + dd t)r ds(on) + k(v in ) 2 (i max )(c rss )(f osc ) psync = (v in C v out )/v in (i max ) 2 (1 + dd t)r ds(on) where dd t is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the pmain equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the syn- chronous mosfet losses are greatest at high input volt- age or during a short circuit when the duty cycle in this switch in nearly 100%. the term (1 + dd t) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss = q gd / d v ds is usually specified in the mosfet characteristics. the constant k = 2 can be used to estimate the contributions of the two terms in the main switch dissipation equation. if the charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside p-channel efficiency generally improves with a larger mosfet. using asymmetrical mosfets may achieve cost savings or efficiency gains. the schottky diode d1, shown in the typical application on the back page, conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 1a schottky is generally a good size for 4a regulators due to the relatively small average current. larger diodes can result in additional transition losses due to their larger junction capacitance. the diode may be omitted if the efficiency loss can be tolerated. applicatio s i for atio wu uu figure 8. adapter current limiting calculating ic power dissipation the power dissipation of the ltc4007 is dependent upon the gate charge of the top and bottom mosfets (qg1 & qg2 respectively) the gate charge is determined from the manufacturers data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the mosfet. use 6v for the gate voltage swing and v dcin for the drain voltage swing. pd = v dcin ? (f osc (qg1 + qg2) + i q ) example: v dcin = 19v, f osc = 345khz, qg1 = qg2 = 15nc. pd = 235mw adapter limiting an important feature of the ltc4007 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. this allows the prod- uct to operate at the same time that batteries are being charged without complex load management algo rithms. additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. this feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. true analog control is used, with closed-loop feedback ensuring that adapter load current remains within limits. amplifier cl1 in figure 8 senses the voltage across r cl , connected 100mv + 5k clp ltc4007 18 cln 19 4007 f08 15nf + r cl * c in v in cl1 ac adapter input *r cl = 100mv adapter current limit + 16 ltc4007 4007i between the clp and cln pins. when this voltage exceeds 100mv, the amplifier will override programmed charging current to limit adapter current to 100mv/r cl . a lowpass filter formed by 5k w and 15nf is required to eliminate switching noise. if the current limit is not used, clp should be connected to dcin. note that the i cl pin will be asserted when the voltage across r cl is 93mv, before the adapter limit regulation threshold. setting input current limit to set the input current limit, you need to know the minimum wall adapter current rating. subtract 5% for the input current limit tolerance and use that current to deter- mine the resistor value. r cl = 100mv/i lim i lim = adapter min current C (adapter min current ? 5%) table 5. common r cl resistor values adapter r cl value* r cl power r cl power rating (a) ( w ) 1% dissipation (w) rating (w) 1.5 0.06 0.135 0.25 1.8 0.05 0.162 0.25 2 0.045 0.18 0.25 2.3 0.039 0.206 0.25 2.5 0.036 0.225 0.5 2.7 0.033 0.241 0.5 3 0.03 0.27 0.5 * values shown above are rounded to nearest standard value. as is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see table 5). designing the thermistor network there are several networks that will yield the desired function of voltage vs temperature needed for proper operation of the thermistor. the simplest of these is the voltage divider shown in figure 9. unfortunately, since the high/low comparator thresholds are fixed internally, there is only one thermistor type that can be used in this applicatio s i for atio wu uu network; the thermistor must have a high/low resis- tance ratio of 1:7. if this happy circumstance is true for you, then simply set r9 = r th(low) if you are using a thermistor that doesnt have a 1:7 high/ low ratio, or you wish to set the high/low limits to different temperatures, then the more generic network in figure 10 should work. figure 9. voltage divider thermistor network figure 10. general thermistor network ltc4007 ntc r9 9 c7 r th 4007 f09 ltc4007 ntc r9 9 c7 r9a r th 4007 f10 once the thermistor, r th , has been selected and the thermistor value is known at the temperature limits, then resistors r9 and r9a are given by: for ntc thermistors: r9 = 6 r th(low) ? r th(high) /(r th(low) C r th(high) ) r9a = 6 r th(low) ? r th(high) /(r th(low) C 7 ? r th(high) ) for ptc thermistors: r9 = 6 r th(low) ? r th(high) /(r th(high) C r th(low) ) r9a = 6 r th(low) ? r th(high) /(r th(high) C 7 ? r th(low) ) example #1: 10k w ntc with custom limits tlow = 0 c, thigh = 50 c r th = 10k at 25 c, r th(low) = 32.582k at 0 c r th(high) = 3.635k at 50 c r9 = 24.55k ? 24.3k (nearest 1% value) r9a = 99.6k ? 100k (nearest 1% value) 17 ltc4007 4007i applicatio s i for atio wu uu example #2: 100k w ntc tlow = 5 c, thigh = 50 c r th = 100k at 25 c, r th(low) = 272.05k at 5 c r th(high) = 33.195k at 50 c r9 = 226.9k ? 226k (nearest 1% value) r9a = 1.365m ? 1.37m (nearest 1% value) example #3: 22k w ptc tlow = 0 c, thigh = 50 c r th = 22k at 25 c, r th(low) = 6.53k at 0 c r th(high) = 61.4k at 50 c r9 = 43.9k ? 44.2k (nearest 1% value) r9a = 154k sizing the thermistor hold capacitor during the hold interval, c7 must hold the voltage across the thermistor relatively constant to avoid false readings. a reasonable amount of ripple on ntc during the hold interval is about 10mv to 15mv. therefore, the value of c7 is given by: c7 = t hold /(r9/7 ? Cln(1 C 8 ? 15mv/4.5v)) = 10 ? r rt ? 17.5pf/(r9/7 ? C ln(1 C 8 ? 15mv/4.5v) example: r9 = 24.3k r rt = 309k (~2 hour timer) c7 = 0.51 m f ? 0.56 m f (nearest value) disabling the thermistor function if the thermistor is not needed, connecting a resistor between dcin and ntc will disable it. the resistor should be sized to provide at least 10 m a with the minimum voltage applied to dcin and 10v at ntc. generally, a 301k resistor will work for dcin less than 15v. a 499k resistor is recommended for dcin greater than 15v. conditioning depleted batteries severely depleted batteries, with less than 2.5v/cell, should be conditioned with a trickle charge to prevent possible damage. this trickle charge is typically 10% of the 1c rate of the battery. the ltc4007 can automatically trickle charge depleted batteries using the circuit in figure 11. if the battery voltage is less than 2.5v/cell (2.44v/cell if chem is low) then the lobat indicator will be low and q4 is off. this programs the charging current with r prog = r6 + r14. charging current is approximately 300ma. when the cell voltage becomes greater than 2.5v the lobat indicator goes high, q4 shorts out r13, then r prog = r6. charging current is then equal to 3a. pcb layout considerations for maximum efficiency, the switch node rise and fall times should be minimized. to prevent magnetic and electrical field radiation and high frequency resonant prob- lems, proper layout of the components connected to the ic is essential. (see figure 12.) here is a pcb layout priority list for proper layout. layout the pcb using this specific order. 1. input capacitors need to be placed as close as possible to switching fets supply and ground connections. shortest copper trace connections possible. these parts must be on the same layer of copper. vias must not be used to make this connection. 2. the control ic needs to be close to the switching fets gate terminals. keep the gate drive signals short for a clean fet drive. this includes ic supply pins that con- nect to the switching fet source pins. the ic can be placed on the opposite side of the pcb relative to above. 3. place inductor input as close as possible to switching fets output connection. minimize the surface area of this trace. make the trace width the minimum amount needed to support currentno copper fills or pours. avoid running the connection using multiple layers in parallel. minimize capacitance from this node to any other trace or plane. 4. place the output current sense resistor right next to the inductor output but oriented such that the ics current sense feedback traces going to resistor are not long. the feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. locate any filter component on these traces next to the ic and not at the sense resistor location. 18 ltc4007 4007i figure 11. circuit application (16.8v/3a) to automatically trickle charge depleted batteries 3c4c chem lobat i cl acp shdn fault chg flag ntc r t lobat i cl acp shdn fault chg flag dcin infet clp cln tgate bgate pgnd csp bat prog ith gnd ltc4007 r9 32.4k 1% r t 309k 1% c7 0.47 f thermistor timing resistor (~2 hours) r12 100k r11 100k r10 100k v logic * * dcin 0v to 20v 3a c1 0.1 f q3 input switch c4 15nf q1 q2 d1 c2 20 f l1 15 h 3a r1 4.9k 1% r4 3.01k 1% r5 3.01k 1% r sense 0.033 1% r cl 0.033 1% c3 20 f *pin open d1: mbrm140t3 q1: si4431ady q2: fdc645n q4: 2n7002 or bss138 bat monitor (charging current monitor) system load c6 0.12 f r7 6.04k 1% r14 73.2k 1% c5 0.0047 f 4007 f11 r6 26.7k 1% q4 5. place output capacitors next to the sense resistor output and ground. 6. output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. general rules 7. connection of switching ground to system ground or internal ground plane should be single point. if the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. route analog ground as a trace tied back to ic ground (analog ground pin if present) before connecting to any other ground. avoid using the system ground plane. cad trick: make analog ground a separate ground net and use a 0 w resistor to tie analog ground to system ground. 9. a good rule of thumb for via count for a given high current path is to use 0.5a per via. be consistent. 10. if possible, place all the parts listed above on the same pcb layer. 11. copper fills or pours are good for all power connec- tions except as noted above in rule 3. you can also use copper planes on multiple layers in parallel toothis helps with thermal management and lower trace in- ductance improving emi performance further. 12. for best current programming accuracy provide a kelvin connection from r sense to csp and bat. see figure 12 as an example. it is important to keep the parasitic capacitance on the r t , csp and bat pins to a minimum. the traces connecting these pins to their respective resistors should be as short as possible. applicatio s i for atio wu uu 19 ltc4007 4007i package descriptio n u figure 12. high speed switching path figure 13. kelvin sensing of charging current 4007 f12 v bat l1 v in high frequency circulating path bat switch node c2 c3 d1 csp 4007 f13 direction of charging current r sense bat applicatio s i for atio wu uu gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .337 ?.344* (8.560 ?8.738) gn24 (ssop) 0502 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 17 18 19 20 21 22 23 24 15 14 13 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 20 ltc4007 4007i linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0103 1.5k ? printed in usa related parts part number description comments lt ? 1511 constant-current/constant-voltage 3a battery high efficiency current mode pwm with 4a internal switch charger with input current limiting lt1513 sepic constant- or programmable-current/ charger input voltage may be higher, equal to or lower than battery voltage; constant-voltage battery charger charges any number of cells up to 20v, 500khz switching frequency lt1571 1.5a switching charger 1- or 2-cell li-ion, 500khz or 200khz switching frequency, termination flag ltc1628-pg 2-phase, dual synchronous step-down controller minimizes c in and c out , power good output, 3.5v v in 36v ltc1709 2-phase, dual synchronous step-down controller up to 42a output, minimum c in and c out , uses smallest components for with vid intel and amd processors ltc1729 lt1769 2a switching battery charger constant-current/constant-voltage switching regulator, input current limiting maximizes charge current ltc1778 wide operating range, no r sense synchronous 2% to 90% duty cycle at 200khz, stable with ceramic c out step-down controller LTC1960 dual battery charger/selector with spi interface simultaneous charge or discharge of two batteries, dac programmable current and voltage, input current limiting maximizes charge current ltc3711 no r sense tm synchronous step-down controller 3.5v v in 36v, 0.925v v out 2v, for transmeta, amd and intel with vid mobile processors ltc4006 small, high efficiency, fixed voltage, constant-current/constant-voltage switching regulator with termination lithium-ion battery charger timer, ac adapter current limit and thermistor sensor in a small 16-pin package ltc4008 high efficiency, programmable voltage/current constant-current/constant-voltage switching regulator, resistor voltage/ battery charger current programming, ac adapter current limit and thermistor sensor no r sense is a trademark of linear technology corporation. 12.6v, 4a li-ion battery charger 3c4c chem lobat i cl acp shdn fault chg flag ntc r t lobat i cl acp shdn fault chg flag dcin infet clp cln tgate bgate pgnd csp bat prog ith gnd ltc4007 r9 32.4k 1% r rt 309k 1% c7 0.47 f thermistor 10k ntc timing resistor (~2 hours) r12 100k * r11 100k r10 100k v logic dcin 0v to 20v 3a c1 0.1 f q3 input switch c4 15nf q1 q2 d1 c2 20 f l1 10 h 4a r1 4.9k 1% r4 3.01k 1% r5 3.01k 1% r sense 0.025 1% r cl 0.033 1% c3 20 f bat charging current monitor system load c6 0.12 f r7 6.04k 1% r prog 26.7k 1% c5 0.0047 f *pin open d1: mbrs130t3 q1: si4431ady q2: fdc645n 4007 ta02 typical applicatio u |
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